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M41T315Y* M41T315V/W
Serial Access Phantom RTC Supervisor
FEATURES SUMMARY

3.0V, 3.3V, OR 5V OPERATING VOLTAGE REAL TIME CLOCK KEEPS TRACK OF TENTHS/HUNDREDTHS OF SECONDS, SECONDS, MINUTES, HOURS, DAYS, DATE OF THE MONTH, MONTHS, AND YEARS AUTOMATIC LEAP YEAR CORRECTION VALID UP TO 2100 AUTOMATIC SWITCH-OVER AND DESELECT CIRCUITRY CHOICE OF POWER-FAIL DESELECT VOLTAGES: (VPFD = Power-fail Deselect Voltage) - M41T315Y: VCC = 4.5 to 5.5V 4.25V VPFD 4.50V - M41T315V: VCC = 3.0 to 3.6V 2.80V VPFD 2.97V - M41T315W: VCC = 2.7 to 3.3V 2.60V VPFD 2.70V NO ADDRESS SPACE REQUIRED TO COMMUNICATE WITH RTC PROVIDES NONVOLATILE SUPERVISOR FUNCTIONS FOR BATTERY BACKUP OF SRAM FULL 10% VCC OPERATING RANGE INDUSTRIAL OPERATING TEMPERATURE RANGE (-40 to +85C) ULTRA-LOW BATTERY SUPPLY CURRENT OF 500nA (max) OPTIONAL PACKAGING INCLUDES A 28LEAD SOIC and SNAPHAT(R) TOP (to be ordered separately) SNAPHAT PACKAGE PROVIDES DIRECT CONNECTION FOR A SNAPHAT TOP, WHICH CONTAINS THE BATTERY AND CRYSTAL
Figure 1. 16-pin SOIC Package
16 1
SO16 (MQ)
Figure 2. 28-pin SOIC Package
SNAPHAT (SH) Battery/Crystal
28 1
SOH28 (MH)
* Contact Local Sales Office
June 2004 1/24
M41T315Y*, M41T315V, M41T315W
TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 1. 16-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2. 28-pin SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Figure 3. Table 1. Figure 4. Figure 5. Figure 6. Figure 7. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 16-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 28-pin SOIC Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 M41T315Y/V/W to RAM/Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 2. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Non-volatile Supervisor Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 8. READ Mode Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 9. WRITE Mode Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 3. AC Electrical Characteristics (M41T315Y) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Table 4. AC Electrical Characteristics (M41T315V/W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 10.Comparison Register Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 CLOCK OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clock Register Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 AM-PM/12/24 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Oscillator and Reset Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Zero Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Table 5. RTC Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 11.Reset Pulse Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 7. DC and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 12.AC Testing Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 8. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 9. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 10. Crystal Electrical Characteristics (Externally Supplied) . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 13.Power Down/Up Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Table 11. Power Down/Up Trip Points DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
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M41T315Y*, M41T315V, M41T315W
Figure 14.SO16 - 16-lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . 18 Table 12. SO16 - 16-lead Plastic Small Outline (150 mils body width), Package Mech. Data . . . . 18 Figure 15.SOH28 - 28-lead Plastic Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . . . . . 19 Table 13. SOH28 - 28-lead Plastic Small Outline, Package Mechanical Data . . . . . . . . . . . . . . . . 19 Figure 16.SH - 4-pin SNAPHAT Housing for 48mAh Battery and Crystal, Package Outline . . . . . 20 Table 14. SH - 4-pin SNAPHAT Housing for 48mAh Battery and Crystal, Package Mech. Data . . 20 Figure 17.SH - 4-pin SNAPHAT Housing for 120mAh Battery and Crystal, Package Outline . . . . 21 Table 15. SH - 4-pin SNAPHAT Housing for 120mAh Battery and Crystal, Package Mech. Data . 21 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 16. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Table 17. SNAPHAT Battery Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 18. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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M41T315Y*, M41T315V, M41T315W
SUMMARY DESCRIPTION
The M41T315Y/V/W RTC Supervisor is a combination of a CMOS TIMEKEEPER(R) and a nonvolatile memory supervisor. Power is constantly monitored by the memory supervisor. In the event of power instability or absence, an external battery maintains the timekeeping operation and provides power for a CMOS static RAM by switching on and invoking write protection to prevent data corruption in the memory and RTC. The clock keeps track of tenths/hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The last day of the month is automatically adjusted for months with less than 31 days, including leap year correction. The clock operates in one of two formats: - a 12-hour mode with an AM/PM indicator; or - a 24-hour mode The nonvolatile supervisor supplies all the necessary support circuitry to convert a CMOS RAM to a nonvolatile memory. The M41T315Y/V/W can be interfaced with RAM without leaving gaps in memory. The M41T315Y/V/W is supplied in a 28-lead SOIC SNAPHAT(R) package (which integrates both crystal and battery in a single SNAPHAT top) or a-16 pin SOIC. The 28-pin, 330mil SOIC provides sockets with gold plated contacts at both ends for direct connection to a separate SNAPHAT housing containing the battery and crystal. The unique design allows the SNAPHAT battery/crystal package to be mounted on top of the SOIC package after the completion of the surface mount process. Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal damage due to the high temperatures required for device surface-mounting. The SNAPHAT housing is also keyed to prevent reverse insertion. The 28-pin SOIC and battery/crystal packages are shipped separately in plastic anti-static tubes or in Tape & Reel form. For the 28-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is "M4TXX-BR12SH" (see Table 17., page 22). Caution: Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the lithium button-cell battery.
Figure 3. Logic Diagram
Note: 1. For 16-pin SOIC only
Table 1. Signal Names
VCCI VCCO
XI-XO D Q 32.768 kHz Crystal Connection Data Input Data Output Reset Input Chip Enable Output Chip Enable Input Battery Input Output Enable Input WRITE Enable Input Switched Supply Voltage Output Supply Voltage Input Ground Not Connected Internally Don't Use
D XI
(1)
Q
RST
(1)
XO WE CEI OE RST
CEO M41T315Y M41T315V M41T315W
CEO CEI VBAT OE WE VCCO
VBAT
(1)
VSS
AI03902
VCCI VSS NC DU
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M41T315Y*, M41T315V, M41T315W
Figure 4. 16-pin SOIC Connections Figure 5. 28-pin SOIC Connections
WE NC NC NC NC NC NC VSS NC NC D Q NC VSS 1 2 3 4 5 6 M41T315Y 7 M41T315V 8 M41T315W 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCCI NC NC VCCO DU NC RST NC OE NC NC CEI CEO NC
XI XO WE VBAT(1) VSS D Q VSS
16 1 2 15 3 14 4 M41T315Y 13 M41T315V 5 M41T315W 12 6 11 7 10 8 9
VCCI VCCO DU RST OE CEI CEO NC
AI03909
AI03910
Note: 1. Should be tied to VSS if not used.
Figure 6. Block Diagram
XO 32,768 Hz CRYSTAL CEO CEI OE WE RST CONTROL LOGIC READ WRITE POWER-FAIL TIMEKEEPER REGISTER XI CLOCK/CALENDAR LOGIC UPDATE
ACCESS ENABLE SEQUENCE DETECTOR
COMPARISON REGISTER
D Q
I/O BUFFERS
DATA INTERNAL VCC POWER-FAIL DETECT LOGIC
VCCI
VCCO
VBAT
AI03636B
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M41T315Y*, M41T315V, M41T315W
Figure 7. M41T315Y/V/W to RAM/Clock Interface
A0-An
A0-An
DATA I/O
D0-D7
WE OE
WE OE CE
CMOS SRAM VCC
CEO OE WE CE RST CEI RST VBAT X0 BAT
+
VCCO
D M41T315Y/V/W Q
VCC
VCCI
X1 VSS
VSS
32.768 Hz CRYSTAL
AI04258
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M41T315Y*, M41T315V, M41T315W
OPERATION
Figure 6., page 5 illustrates the main elements of the device. The following paragraphs describe the signals and functions. Communication with the clock is established by pattern recognition of a serial bit stream of 64 bits which must be matched by executing 64 consecutive WRITE cycles containing the proper data on data in (D). All accesses which occur prior to recognition of the 64-bit pattern are directed to memory via the chip enable output pin (CEO). After recognition is established, the next 64 READ or WRITE Cycles either extract or update data in the clock and CEO remains high during this time, disabling the connected memory (see Table 2., page 7). Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of chip enable input (CEI), output enable (OE), and WRITE enable (WE). Initially, a READ cycle using the CEI and OE control of the clock starts the pattern recognition sequence by moving the pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive WRITE cycles are executed using the CEI and WE control of the clock. These 64 WRITE cycles are used only to gain access to the clock. When the first WRITE cycle is executed, it is compared to the first bit of the 64-bit comparison regTable 2. Operating Modes
Mode Deselect WRITE READ READ Deselect Deselect VCC 4.5 to 5.5V or 3.0 to 3.6V or 2.7 to 3.3V VSO to VPFD (min)(1) VSO(1) CEI VIH VIL VIL VIL X X OE X X VIL VIH X X WE X VIL VIH VIH X X D Hi-Z DIN Hi-Z Hi-Z Hi-Z Hi-Z Q Hi-Z Hi-Z DOUT Hi-Z Hi-Z Hi-Z Power Standby Active Active Active CMOS Standby Battery Back-up Mode
ister. If a match is found, the pointer increments to the next location of the comparison register and awaits the next WRITE cycle. If a match is not found, the pointer does not advance and all subsequent WRITE cycles are ignored. If a READ cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 WRITE cycles as described above until all the bits in the comparison register have been matched (see Figure 10., page 11.) With a correct match for 64 bits, access to the registers is enabled and data transfer to or from the timekeeping registers may proceed. The next 64 cycles will cause the device to either receive data on D, or transmit data on Q, depending on the level of OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CEI cycles without interrupting the pattern recognition sequence or data transfer sequence to the device. For a SO16 pin package, a standard 32.768 kHz quartz crystal can be directly connected to the M41T315Y/V/W via pins 1 and 2 (XI, XO). The crystal selected for use should have a specified load capacitance (CL) of 12.5 pF (see Table 10., page 17).
Note: X = VIH or VIL; VSO = Battery Back-up Switchover Voltage. Note: 1. See Table 11., page 17 for details.
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M41T315Y*, M41T315V, M41T315W
Non-volatile Supervisor Operation A switch is provided to direct power from the battery input or VCCI to VCCO with a maximum voltage drop of 0.3 Volts. The VCCO output pin is used to supply uninterrupted power to CMOS SRAM. The M41T315Y/V/W safeguards the clock and RAM data by power-fail detection and write protection. Power-fail detection occurs when VCCI falls below VPFD which is set by an internal bandgap reference. The M41T315Y/V/W constantly monitors the VCCI supply pin. When VCCI is less than VPFD, Figure 8. READ Mode Waveforms
WE tRC tCW tCO CEI tOW tOD tRR
power-fail circuitry forces the chip enable output (CEO) to VCCI or VBAT-0.2 volts for external RAM write protection. During nominal supply conditions, CEO will track CEI with a propagation delay. Internally, the M41T315Y/V/W aborts any data transfer in progress without changing any of the device registers and prevents future access until VCCI exceeds VPFD. Figure 7., page 6 illustrates a typical RAM/clock interface.
OE tOE tOEE tCOE Q DATA OUTPUT VALID AI04259 tODO
Figure 9. WRITE Mode Waveforms
OE tWC tWP tWR
WE tCW CEI t DH tDS D DATA INPUT STABLE
AI04261
tWR
tDH
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M41T315Y*, M41T315V, M41T315W
Table 3. AC Electrical Characteristics (M41T315Y)
Symbol tAVAV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tRC tCO tOE tCOE tOEE tOD tODO tRR tELEH tGLGH tAVAV tWLWH tEHAX tWHAX tDVEH tDVWH tEHDX tWHDX tCW tOW tWC tWP tWR(2) tDS(3) tDH(3) tRST Parameter(1) READ Cycle Time CEI Access Time OE Access Time CEI to Output Low Z OE to Output Low Z CEI to Output High Z OE to Output High Z READ Recovery CEI Pulse Width OE Pulse Width WRITE Cycle WRITE Pulse Width WRITE Recovery Data Setup Data Hold Time RST Pulse Width 10 55 55 65 55 10 30 0 65 5 5 25 25 Min 65 55 55 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 4.5 to 5.5V (except where noted). 2. tWR is a function of the latter occurring edge of WE or CEI. 3. tDH and tDS are functions of the first occurring edge of WE or CEI in RAM mode.
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M41T315Y*, M41T315V, M41T315W
Table 4. AC Electrical Characteristics (M41T315V/W)
Symbol tAVAV tELQV tGLQV tELQX tGLQX tEHQZ tGHQZ tRC tCO tOE tCOE tOEE tOD tODO tRR tELEH tGLGH tAVAV tWLWH tEHAX tWHAX tDVEH tDVWH tEHDX tWHDX tCW tOW tWC tWP tWR(2) tDS(3) tDH(3) tRST Parameter(1) READ Cycle Time CEI Access Time OE Access Time CEI to Output Low Z OE to Output Low Z CEI to Output High Z OE to Output High Z READ Recovery CEI Pulse Width OE Pulse Width WRITE Cycle WRITE Pulse Width WRITE Recovery Data Setup Data Hold Time RST Pulse Width 20 65 60 85 60 25 35 5 85 5 5 30 30 Min 85 85 85 Typ Max Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Note: 1. Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 2.7 to 3.6V (except where noted). 2. tWR is a function of the latter occurring edge of WE or CEI. 3. tDH and tDS are functions of the first occurring edge of WE or CEI in RAM mode.
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M41T315Y*, M41T315V, M41T315W
Figure 10. Comparison Register Definition
Hex Value C5
7 BYTE 0 1
6 1
5 0
4 0
3 0
2 1
1 0
0 1
BYTE 1
0
0
1
1
1
0
1
0
3A
BYTE 2
1
0
1
0
0
0
1
1
A3
BYTE 3
0
1
0
1
1
1
0
0
5C
BYTE 4
1
1
0
0
0
1
0
1
C5
BYTE 5
0
0
1
1
1
0
1
0
3A
BYTE 6
1
0
1
0
0
0
1
1
A3
BYTE 7
0
1
0
1
1
1
0
0
5C AI04262
Note: Pattern recognition in "hex" is C5, 3A, A3, 5C, C5, 3A, A3, and 5C. The odds of this pattern being accidentally duplicated and sending aberrant entries to the RTC is less than 1 in 1019. This pattern is sent to the clock LSB to MSB.
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M41T315Y*, M41T315V, M41T315W
Data Retention Most low power SRAMs on the market today can be used with the M41T315Y/V/W. There are, however some criteria which should be used in making the final choice of an SRAM to use. The SRAM must be designed in a way where the chip enable input disables all other inputs to the SRAM. This allows inputs to the M41T315Y/V/W and SRAMs to be Don't Care once VCCI falls below VPFD(min). The SRAM should also guarantee data retention down to VCC=2.0 volts. The chip enable access time must be sufficient to meet the system needs with the chip enable output propagation delays included. If the SRAM includes a second chip enable pin (E2), this pin should be tied to VOUT. If data retention lifetime is a critical parameter for the system, it is important to review the data retention current specifications for the particular
SRAMs being evaluated. Most SRAMs specify a data retention current at 3.0 volts. Manufacturers generally specify a typical condition for room temperature along with a worst case condition (generally at elevated temperatures). The system level requirements will determine the choice of which value to use. The data retention current value of the SRAMs can then be added to the IBAT value of the M41T315Y/V/W to determine the total current requirements for data retention. The available battery capacity for the SNAPHAT(R) of your choice can then be divided by this current to determine the amount of data retention available (see Table 17., page 22). For a further more detailed review of lifetime calculations, please see Application Note AN1012.
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M41T315Y*, M41T315V, M41T315W
CLOCK OPERATION
Clock Register Information Clock information is contained in eight registers of 8 bits, each of which is sequentially accessed 1 bit at a time after the 64-bit pattern recognition sequence has been completed. When updating the clock registers, each must be handled in groups of 8 bits. Writing and reading individual bits within a register could produce erroneous results. These READ/WRITE registers are defined in Table 5., page 13. Data contained in the clock registers is in binary coded decimal format (BCD). Reading and writing the registers is always accomplished by stepping though all eight registers, starting with Bit 0 of Register 0 and ending with Bit 7 of Register 7. AM-PM/12/24 Mode Bit 7 of the hours register is defined as the 12-hour or 24-hour mode select bit. When high, the 12hour mode is selected. In the 12-hour mode, Bit 5 is the AM/PM bit with logic high being PM. In the 24-hour mode, Bit 5 is the second 10-hour bit (2023 hours). Table 5. RTC Register Map
Register 0 1 2 3 4 5 6 7
Keys: A/P = AM/PM Bit 12/24 = 12 or 24-hour mode Bit OSC = Oscillator Bit RST = Reset Bit 0 = Must be set to '0'
Oscillator and Reset Bits Bits 4 and 5 of the day register are used to control the reset and oscillator functions. Bit 4 controls the reset pin input. When the Reset Bit is set to logic '1,' the reset input pin is ignored. When the Reset Bit is set to logic '0,' a low input on the reset pin will cause the device to abort data transfer without changing data in the timekeeping registers. Reset operates independently of all other inputs. Bit 5 controls the oscillator. When set to logic '0,' the oscillator turns on and the real time clock/calendar begins to increment. Zero Bits Registers 1, 2, 3, 4, 5, and 6 contain one (1) or more bits that will always read logic '0.' When writing to these locations, either a logic '1' or '0' is acceptable.
D7
D6
D5
D4
D3
D2
D1
D0
Function/Range BCD Format Seconds Seconds Minutes Hours Day Date Month Year 00-99 00-59 00-59 01-12/ 00-23 01-7 01-31 01-12 00-99
0.1 Seconds 0 0 12/24 0 0 0 0 0 0 0 10 Years 0 10 Seconds 10 Minutes 10 / A/P OSC Hrs RST 0
0.01 Seconds Seconds Minutes Hours (24 Hour Format) Day of the Week Date: Day of the Month Month Year
10 date 10M
Figure 11. Reset Pulse Waveform
tRST
RST
AI04260
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M41T315Y*, M41T315V, M41T315W
MAXIMUM RATING
Stressing the device above the rating listed in the "Absolute Maximum Ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is Table 6. Absolute Maximum Ratings
Symbol TA TSTG TSLD
(1)
not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
Parameter Operating Temperature Storage Temperature (VCC, Oscillator Off) Lead Solder Temperature for 10 seconds Supply Voltage (on any pin relative to Ground) Input or Output Voltages Output Current Power Dissipation M41T315Y M41T315V/W SNAPHAT SOIC
(R)
Value -40 to +85 -40 to +85 -55 to +125 260 -0.3 to +7.0 -0.3 to +4.6 -0.3 to VCC + 0.3 20 1
Unit C C C C V V V mA W
VCCI VIO IO PD
Note: 1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225C (total thermal budget not to exceed 180C for between 90 to 150 seconds). 2. For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260C (total thermal budget not to exceed 245C for greater than 30 seconds).
CAUTION: Negative undershoots below -0.3V are not allowed on any pin while in the Battery Back-up mode. CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
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M41T315Y*, M41T315V, M41T315W
DC AND AC PARAMETERS
This section summarizes the operating and measurement conditions, as well as the DC and AC characteristics of the device. The parameters in the following DC and AC Characteristic tables are derived from tests performed under the MeasureTable 7. DC and AC Measurement Conditions
Parameter VCC Supply Voltage Ambient Operating Temperature Load Capacitance (CL) Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages M41T315Y 4.5 to 5.5V -40 to 85C 100pF 5ns 0 to 3V 1.5V M41T315V/W 2.7 to 3.6V -40 to 85C 50pF 5ns 0 to 3V 1.5V
ment Conditions listed in the relevant tables. Designers should check that the operating conditions in their projects match the measurement conditions when using the quoted parameters.
Figure 12. AC Testing Load Circuit
DEVICE UNDER TEST
400
CL
2.0V
CL includes JIG capacitance
AI04255
Note: 50pF for M41T315V.
Table 8. Capacitance
Symbol CIN CIO(3) Parameter(1,2) Input Capacitance Input / Output Capacitance Min Max 10 10 Unit pF pF
Note: 1. Effective capacitance measured with power supply at 5V; sampled only; not 100% tested. 2. At 25C, f = 1MHz. 3. Outputs were deselected.
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M41T315Y*, M41T315V, M41T315W
Table 9. DC Characteristics
M41T315Y Sym Parameter Test Condition(1) Min IIL(2) IOL ICC1(3) ICCO1(4) ICC2(3) ICC3(3) VIL(5) VIH(5) VOL(6) VOH(6) VPFD VSO VBAT VCEO Input Leakage Current Output Leakage Current Supply Current VCC Power Supply Current Supply Current (TTL Standby) VCC Power Supply Current Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Power Fail Deselect Battery Back-up Switchover Battery Voltage CEO Output Voltage VBAT = 3.0V TA = 25C VCC = 0V VCCO = VBAT - 0.2V 2.5 VCCI - 0.2 or VBAT - 0.2 0.5 IOL = 4.0 mA IOH = -1.0 mA 2.4 4.25 VBAT 3.7 2.5 VCCI - 0.2 or VBAT - 0.2 0.5 4.50 VCC0 = VCCI - 0.3 CEI = VIH CEI = VCCI - 0.2 -0.3 2.2 0V VIN VCC 0V VOUT VCC -65 Typ Max 1 1 10 150 3 1 0.8 VCC + 0.3 0.4 2.4 2.80 (V) 2.60 (W) 2.5 3.7 2.97 (V) 2.70 (W) -0.3 2.0 Min M41T315V/W -85 Typ Max 1 1 6 100 2 1 0.6 VCC + 0.3 0.4 A A mA mA mA mA V V V V V V V V Unit
IBAT(3)
Battery Current
A
Battery Backup ICCO2(7) Current
Note: 1. 2. 3. 4. 5. 6. 7.
100
100
A
Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted). Applies to all input pins except RST, which is pulled internally to VCCI. Measured without RAM connected. ICCO1 is the maximum average load current the device can supply to external memory. Voltages are referenced to Ground. Measured with load shown in Figure 12., page 15. ICCO2 is the maximum average load current that the device can supply to memory in the battery backup mode.
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M41T315Y*, M41T315V, M41T315W
Table 10. Crystal Electrical Characteristics (Externally Supplied)
Symbol Parameter(1,2) Resonant Frequency Series Resistance Load Capacitance 12.5 Min Typ 32.768 60 Max Unit kHz k pF
fO
RS CL
Note: 1. These values are externally supplied. STMicroelectronics recommends the KDS DT-38: 1TA/1TC252E127, Tuning Fork Type (thruhole) or the DMX-26S: 1TJS125FH2A212, (SMD) quartz crystal for industrial temperature operations. KDS can be contacted at kouhou@kdsj.co.jp or http://www.kdsj.co.jp for further information on this crystal type. Note: 1. Load capacitors are integrated within the M41T315Y/V/W. Circuit board layout considerations for the 32.768kHz crystal of minimum trace lengths and isolation from RF generating signals should be taken into account.
Figure 13. Power Down/Up Mode AC Waveforms
VCC VPFD (max) VPFD (min) VSO tFB tF tPF CEI tPD CEO
AI04257
tR tREC DON'T CARE
VBAT - 0.2V
VBAT - 0.2V
tPD
Table 11. Power Down/Up Trip Points DC Characteristics
Symbol tREC tF tFB tR tPF tPD(3,4)
Note: 1. 2. 3. 4.
Parameter(1,2) VPFD (max) to CEI low VPFD (max) to VPFD (min) VCC Fall Time VPFD (min) to VSO VCC Fall Time VPFD (min) to VPFD (max) VCC Rise Time CEI High to Power-Fail M41T315Y CEI Propagation Delay M41T315V/W
Min 1.5 300 10 0 0
Max 2.5
Unit ms
s s s s
10 15
ns ns
Valid for Ambient Operating Temperature: TA = -40 to 85C; VCC = 4.5 to 5.5V or 2.7 to 3.6V (except where noted). Measured at 25C. Measured with load shown in Figure 12., page 15. Input pulse rise and fall times equal 10ns
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M41T315Y*, M41T315V, M41T315W
PACKAGE MECHANICAL INFORMATION
Figure 14. SO16 - 16-lead Plastic Small Outline, Package Outline
A2 B e D
A C CP
N
E
1
H A1 L
SO-b
Note: Drawing is not to scale.
Table 12. SO16 - 16-lead Plastic Small Outline (150 mils body width), Package Mech. Data
mm Symb Typ A A1 A2 B C D E e H L a N CP 1.27 0.35 0.19 9.80 3.30 - 5.80 0.40 0 16 0.10 0.10 Min Max 1.75 0.25 1.60 0.46 0.25 10.00 4.00 - 6.20 1.27 8 0.050 0.014 0.007 0.386 0.150 - 0.228 0.016 0 16 0.004 0.004 Typ Min Max 0.069 0.010 0.063 0.018 0.010 0.394 0.158 - 0.244 0.050 8 inches
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M41T315Y*, M41T315V, M41T315W
Figure 15. SOH28 - 28-lead Plastic Small Outline, Package Outline
A2 B e
A C eB CP
D
N
E
H A1 L
1 SOH-A
Note: Drawing is not to scale.
Table 13. SOH28 - 28-lead Plastic Small Outline, Package Mechanical Data
mm Symb Typ A A1 A2 B C D E e eB H L a N CP 1.27 0.05 2.34 0.36 0.15 17.71 8.23 - 3.20 11.51 0.41 0 28 0.10 Min Max 3.05 0.36 2.69 0.51 0.32 18.49 8.89 - 3.61 12.70 1.27 8 0.050 0.002 0.092 0.014 0.006 0.697 0.324 - 0.126 0.453 0.016 0 28 0.004 Typ Min Max 0.120 0.014 0.106 0.020 0.012 0.728 0.350 - 0.142 0.500 0.050 8 inches
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M41T315Y*, M41T315V, M41T315W
Figure 16. SH - 4-pin SNAPHAT Housing for 48mAh Battery and Crystal, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note: Drawing is not to scale.
Table 14. SH - 4-pin SNAPHAT Housing for 48mAh Battery and Crystal, Package Mech. Data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 14.22 15.55 3.20 2.03 6.73 6.48 Min Max 9.78 7.24 6.99 0.38 0.56 21.84 14.99 15.95 3.61 2.29 Typ Min 0 0.265 0.255 0 0.018 0.835 0.560 .6122 0.126 0.080 Max 0.385 0.285 0.275 0.015 0.022 0.860 0.590 .6280 0.142 0.090 inches
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M41T315Y*, M41T315V, M41T315W
Figure 17. SH - 4-pin SNAPHAT Housing for 120mAh Battery and Crystal, Package Outline
A1
A2 A A3
eA D
B eB
L
E
SHTK-A
Note: Drawing is not to scale.
Table 15. SH - 4-pin SNAPHAT Housing for 120mAh Battery and Crystal, Package Mech. Data
mm Symb Typ A A1 A2 A3 B D E eA eB L 0.46 21.21 17.27 15.55 3.20 2.03 8.00 7.24 Min Max 10.54 8.51 8.00 0.38 0.56 21.84 18.03 15.95 3.61 2.29 Typ Min 0 0.315 0.285 0 0.018 0.835 0.680 .6122 0.126 0.080 Max 0.415 0.335 0.315 0.015 0.022 0.860 0.710 .6280 0.142 0.090 inches
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M41T315Y*, M41T315V, M41T315W
PART NUMBERING
Table 16. Ordering Information Scheme
Example: Device Type M41T Supply Voltage and Write Protect Voltage 315Y(1) = VCC = 4.5 to 5.5V; VPFD = 4.25 to 4.50V 315V = VCC = 3.0 to 3.6V; VPFD = 2.80 to 2.97V 315W = VCC = 2.7 to 3.3V; VPFD = 2.60 to 2.70V Speed -65 = 65ns (315Y) -85 = 85ns (315V/W) Package MH(2) = SOH28 MQ = SO16 Temperature Range 6 = -40 to 85C Shipping Method For SOH28: blank = Tubes (Not for New Design - Use E) E = Lead-free Package (ECO PACK(R)), Tubes M41T 315Y -65 MH 6 E
F = Lead-free Package (ECO PACK(R)), Tape & Reel TR = Tape & Reel (Not for New Design - Use F) For SO16: blank = Tubes (Not for New Design - Use E) E = Lead-free Package (ECO PACK(R)), Tubes
F = Lead-free Package (ECO PACK(R)), Tape & Reel TR = Tape & Reel (Not for New Design - Use F)
Note: 1. Contact Local Sales Office 2. The SOIC package (SOH28) requires the SNAPHAT(R) battery package which is ordered separately under the part number "M4TXXBR12SHX" in plastic tube or "M4TXX-BR12SHXTR" in Tape & Reel form (see Table 17). Caution: Do not place the SNAPHAT battery package "M4TXX-BR12SH" in conductive foam as it will drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the ST Sales Office nearest you. Table 17. SNAPHAT Battery Table
Part Number M4T28-BR12SH M4T32-BR12SH Description Lithium Battery (48mAh) SNAPHAT Lithium Battery (120mAh) SNAPHAT Package SH SH
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M41T315Y*, M41T315V, M41T315W
REVISION HISTORY
Table 18. Document Revision History
Date June 2001 17-Jul-01 18-Sep-01 27-Sep-01 01-May-02 04-Nov-02 26-Mar-03 08-Jun-04 Rev. # 1.0 1.1 1.2 1.3 1.4 1.5 1.6 2.0 First Issue Basic formatting changes Changed pin 8 in 28-pin to VSS Added ambient temp to DC Characteristics table (Table 9) Modify reflow time and temperature footnote (Table 6) Modify Crystal Electrical Characteristics table footnotes (Table 10); add marketing status (Table 16) Update test condition (Table 9) Reformatted; add Lead-free information (Table 6, 16) Revision Details
M41T315, M41T315Y, M41T315V, M41T315W, 41T315, 41T315Y, 41T315V, 41T315W, T315,SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, SUPERVISOR, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, NVRAM, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, Serial, 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M41T315Y*, M41T315V, M41T315W
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2004 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore Spain - Sweden - Switzerland - United Kingdom - United States www.st.com
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